University of Tokyo (1st visit)

Host: Prof Kunihiro Asada

Prof Asada [http://www.mos.t.u-tokyo.ac.jp] is professor of electronics at the University of Tokyo [http://www.u-tokyo.ac.jp/] and, as head of the VLSI Design and Education Centre (VDEC) [http://www.vdec.u-tokyo.ac.jp/English/], an influential figure in the field of VLSI design within Japan. VDEC is a 100% government-funded organisation established in 1996 to promote VLSI education and research within Japanese universities. Prof Asada mentioned that there is a similar organisation in Taiwan [CIC - Chip Implementation Centre - http://www.cic.edu.tw/] that is also 100% government-funded, and also one in Korea [IDEC – IC Design Education Centre - http://idec.kaist.ac.kr/English/index.htm]. He added that chip fabrication costs in IDEC, CIC and VDEC are met differently; in IDEC they are borne by industry, in CIC they are met by the government, and in VDEC they are borne by the users – although the price is low thanks to good will from industry.

Prof Asada subsequently identified the following comparable organisations; MOSIS [http://www.mosis.org/] in the USA, CMP in France, CMC in Canada and Europractice in Belgium. He said that all of these also support chip implementation.

About VDEC

VDEC is a key organisation as far as VLSI design education within Japanese universities is concerned. The following quotations are taken (verbatim) from VDEC’s website...
 

"VLSI Design and Education Center (VDEC), which is located in the University of Tokyo and shared by users all over Japan, was established in May, 1996. As an intellectual education center on VLSI (Very Large Scale Integration) technology, VDEC aims at improvements of instruction on VLSI design and supports on VLSI chip fabrication for national universities, public universities, private universities and colleges in Japan. For these purposes, VDEC performs various kinds of activities including distributing VLSI design information, providing CAD software and licenses and supporting chip fabrications. With helps and supports from universities, related government ministries and semiconductor industry, active services provided by VDEC have been growing extensively since its beginning." "Presently VDEC provides following services to end users from universities and colleges in Japan: Distributing the latest technology information on VLSI design and education. Providing media, licenses and training courses of CAD tools. Supporting VLSI chip fabrications and measurements for academic use. Nowadays, 5 different VLSI fabrication technologies, various kinds of popular CAD software which support Verilog HDL/VHDL simulation, synthesis, layout design and verification for digital/analog VLSIs, and measurement facilities are provided through VDEC. Over 450 research groups from 158 universities in Japan are utilizing the services and supports from VDEC. Totally more than 3100 CAD software licenses are being issued from VDEC and its 9 branches in Japan. In 2000, altogether 335 chips were fabricated at various chip foundaries through VDEC." "Mainstream CAD tools from Cadence, Synopsys and Avant! are distributed and supported by VDEC presently. VDEC makes contracts with the CAD vendors and provides 500 to 1000 CAD licenses for each CAD tool to end-users in Japan." "In 2000, about 3100 CAD software licenses were issued to 226 lab users, which increased 19% compared to 1999." "To assist VDEC users with mastering up-to-date LSI design knowledge and techniques, CAD training courses oriented to VDEC users are arranged twice a year by VDEC and CAD vendors such as Cadence, Synopsys and Avant!. Each 3-5 days course including training and lab exercise is provided to over 50 students or researchers free of charge. On the other hand, an education course oriented to company designers is also held once a year. Various kinds of introduction on LSI design, from basic HDL design technology to advanced design examples, are given to 50-100 people at this ‘refresher course’." "Besides in the University of Tokyo, VDEC has established branches in other 9 universities all over Japan to provide CAD software licenses to their nearby users effectively. Various kinds of support, such as measurements and evaluations on fabricated chips, holding seminars on CAD tools and design libraries, are also cooperated by these universities actively." "Each year, a symposium called VDEC Designers' Forum is held in some local university. Young VLSI researchers and designers from universities gathered to communicate their ideas and thoughts on LSI design and education with each other freely at this forum."

Prof Asada explained that VDEC has three main aims...

1. to act as a centre of excellence with regard to VLSI education
2. to provide suitable CAD tools for academic use
3. to act as a silicon chip broker

In connection with the first of these aims Prof Asada said that they have recently published a textbook on VLSI design that embodies their recommended syllabus. In connection with the second aim he said they felt it was important to support industry-standard languages and provide industry-standard EDA tools for the academic community. As far as languages are concerned, they support both VHDL and Verilog HDL, and he said that they are currently looking at C-based languages including Handel-C. VDEC does not support any schematic capture tools. He agreed that a C-based language is the logical next step, and he said that they would support whichever C-based language they felt was closest to being the "industry standard". He said that his colleague Prof Fujita is currently looking at this issue, and added that VDEC also takes into account demand from users. (We subsequently met with Prof Fujita on our second visit to the University of Tokyo, the following week – see second University of Tokyo visit report.)
 

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A few days later, at an evening reception, I happened to meet Dr Satoshi Komatsu who is a research associate at VDEC. He told me that VDEC has a staff of ten, including five professors plus five more junior staff. He said that they support users at other institutions mainly via email. Due to the way the contracts work the EDA vendors only provide technical support to Tokyo University. Users within other universities are not allowed to contact the vendors directly; instead they look to VDEC for support. There are ten VDEC "license servers" within key national universities across the country, and I imagine the way the system works is that these license servers probably ensure that there are never more than 1,000 simultaneous users of a particular EDA tool. Drawing up the contract so that only the University of Tokyo is entitled to support is clearly an effective way for vendors to provide nationwide academic access to software while minimising cost.
 

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How Japanese electronics graduates compare with others

Prof Asada explained that the main focus of VDEC is to support and enhance the university-level education of electronic engineers within Japan. Colin said that he had the impression, from his days at Mitsubishi, that Japanese graduates were often not as well versed with IC design, including the use of industrial-strength EDA tools, as some of their American or European counterparts. Prof Asada didn’t dispute this, and agreed that Japanese universities are "not so mature" in this respect. He added that there was quite a lot of variety; the specialist courses available to students within different university departments depend on the expertise of the faculty within those departments. (When we subsequently met Prof Yasuura at Kyushu University he mentioned that originally only the national universities had access to the facilities provided by VDEC, but that now private universities also have access. Apparently the Ministry of Education changed its stance due to pressure from industry. The argument was that industry needs better-educated electronic engineers from the private universities as well as from the national universities.)

Miscellaneous

Prof Asada pointed out that designers are often reluctant to switch to using a new language. The language they first learn to use is the one they usually feel most comfortable with. On the other hand, if designers see that there is significant potential benefit in using a new language then this will help to overcome this sense of reluctance.

He said that VDEC may need to provide an RTOS (Teal-Time Operating System) for academic users in future.

He mentioned that VDEC organises various seminars and short courses (see the quotations above taken from their website). These sometimes include presentations from EDA vendors, and he suggested that Celoxica might want to participate in these events in the future.

He mentioned that the recent semi-privatisation of national universities means that they are now forced to pay more attention to obtaining industrial funding for research projects.

He suggested that software engineers might be confused at first about the semantics of inline functions in Handel-C, because software engineers normally regard a function as a template that is instantiated upon invocation.

(When I met Dr Komatsu subsequently I mentioned that I was surprised to find so many academics teaching in the universities from which they themselves graduated. He said that this is also true of the Dept. of Electronic Engineering at the University of Tokyo. However, he said that most/all (?) of them had either taught in other universities first or spent time in industry. He added that the University’s rules actually dictate that a post-doctoral researcher like himself must leave the University after a certain period of time.)

Acknowledgement

I am indebted to Prof Asada for his feedback on this report.