The website for Prof Amano’s lab [http://www.am.ics.keio.ac.jp/] lists an impressive array of ongoing projects covering quite a wide variety of topics. Prof Amano said during the meeting that he is currently involved with three projects in which a C-based language such as Handel-C might be usefulŠ
- a "virtual hardware" project (which has support from NEC and Nokia)
- a vision chip project
- a bioinformatics project
We were shown around two laboratories by Naoto Kaneko, one of Prof Amano’s final year undergraduate students. Naoto told us that had lived in America for several years, which explained his fluency in English. He said that he was involved in the virtual hardware project, but he also gave us an outline of several of the other research projects being undertaken within the labs. (We were very impressed by his level of knowledge given that he was still an undergraduate student.)
Each project apparently has something like two PhD students, two Masters students and two undergraduates working on it at any one time. There was clearly a lot of good work going on in two surprisingly small laboratories; Naoto said that students do not have a desk each but have to share the desk space. (I recalled that on my previous visit to Keio University (Bush, 2002), Prof Amano’s colleague Prof Yamamoto had told me that Keio University is probably unique in providing two desks for each doctoral student – so I suppose that explains why the doctoral students, at least, didn’t appear to have dedicated desks in Prof Amano’s research labs.)
Naoto showed us a 16-processor version of "Jump-1" [http://www.am.ics.keio.ac.jp/proj/juten/], a massively parallel processing system being developed in collaboration with six other Japanese universities. This project is apparently funded by the Japanese government, and has been running for around ten years. The system is now in its third generation, and according to their website it uses efficient cache-coherent distributed shared memory and can accommodate over 1,000 processors. (Naoto mentioned that it can accommodate up to 1,024 processors.)
Naoto showed us another project that involved clustering of standard PCs using a switching unit that he said "used to be the world’s fastest switch" [http://www.rwcp.or.jp/lab/opt-hitachi/syokai-E.html]. He said that the switch originated from the government-sponsored "Real World Computing" project [http://www.rwcp.or.jp/home-E.html] but that the network interface cards (?) were designed at Keio University.
The "virtual hardware" project that Naoto is involved with is very much about reconfigurable computing. He said he thought that Prof Amano’s research group was one of the oldest and most active research groups in the field of reconfigurable computing in Japan, although that’s just one aspect of the work they’ve been doing.
Prof Amano had already given us several research publications relating to the virtual hardware project. This project is particularly interesting because its aim is to facilitate the design of customised dataflow computers using multi-context FPGAs. There has been quite a lot of research into dataflow computing over the years, but it remains a rather niche area. It involves translating an algorithm into a directed graph in which the arcs are data flows and the nodes are functional units. As the papers point out, if the directed graph is implemented directly in an FPGA (or a standard ASIC) then its size is limited by the size of the FPGA (or ASIC). One solution to this problem is to partition the graph into subgraphs and to reconfigure an FPGA as necessary during the computation so that each subgraph corresponds to one FPGA configuration. The result, in operation, is a kind of context switching. One of the papers he gave us proposes a new graph partitioning algorithm for just this purpose.
With standard FPGAs, however, the process of reconfiguring (context switching) is relatively slow since it involves inputting a stream of reconfiguration data. According to another of Prof Amano’s papers the time required for this is in the order of one msec. Recently, so-called multi-context FPGAs have been developed; these are chips containing an FPGA plus a set of SRAM slots to store the reconfiguration data. The paper cites a Xilinx "time-multiplex FPGA" that "can hold 8 contexts of configuration data each corresponding to 10,000 gates (400 Control Logic Blocks)"; it has a context switching time of 30 nsec.
Prof Amano’s team are using a new device from NEC that they claim (in the paper) is "the first practical dynamically reconfigurable multi-context device". (As far as I understand it, the figure of 30 nsecs for context switching in the Xilinx chip does not involve *dynamic* reconfiguration; the 8 contexts must be fixed in advance.) The idea is that while one "configuration page" (i.e. subgraph) is active, another configuration page is loaded in parallel into one of the SRAM slots. The operation is analogous to the operation of virtual memory; hence their invention of the phrase "virtual hardware".
Another of the papers he gave us tackles the issue of reducing the loading time of the (dynamic) configuration data via code compression. Since the decoder is within the FPGA, they opt for a compression scheme that requires a small decoder.